1. Field of the Invention
The present invention relates to a clock recovery circuit and a communication device. More particularly, the present invention relates to a clock recovery circuit for adjusting the timing of a clock signal against a data signal and a communication device provided with the clock recovery circuit.
2. Description of the Related Art
A communication LSI employs a clock recovery circuit for adjusting the phase of a clock signal to retrieve a data signal. Such clock recovery circuit compares the phases of the data signal and the clock signal and adjusts the phase of the clock signal using a variable delay circuit. A conventional variable delay circuit is configured with a rough delay circuit whose resolution is low and variable amount is large, a fine delay circuit whose resolution is high and variable amount is the same as the rough delay circuit and a fine delay circuit for compensating the change of the propagation delay time due to the change of the noise or the environmental conditions in real time. As the fine delay circuit for compensating the change of the propagation delay time due to the change of the noise or the environmental conditions in real time, one used together with a voltage controlled oscillator (VCO) of a DLL circuit is proposed (cf. International Publication No. 03/036796).
However, in the fine delay circuit used together with the voltage controlled oscillator (VCO) of the DLL circuit, a variable amount as much as compensating the change of the processes, the noise, and the change of the environmental conditions is needed, so the circuit size increases and besides the degree of the eye opening of the data due to the phase noise of the PLL circuit becomes narrow.